[1]赵旭莹,李桓,王晓琴,等.通信专用新型二维可配置协处理器架构研究[J].哈尔滨工程大学学报,2018,39(12):2011-2016.[doi:10.11990/jheu.201706012]
 ZHAO Xuying,LI Huan,WANG Xiaoqin,et al.A novel two-level reconfigurable communication-specific coprocessor architecture[J].hebgcdxxb,2018,39(12):2011-2016.[doi:10.11990/jheu.201706012]
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通信专用新型二维可配置协处理器架构研究(/HTML)
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《哈尔滨工程大学学报》[ISSN:1006-6977/CN:61-1281/TN]

卷:
39
期数:
2018年12期
页码:
2011-2016
栏目:
出版日期:
2018-12-05

文章信息/Info

Title:
A novel two-level reconfigurable communication-specific coprocessor architecture
作者:
赵旭莹1 李桓1 王晓琴2 王东琳2
1. 中国科学院大学 计算机与控制学院, 北京 100190;
2. 中国科学院自动化研究所 国家专用集成电路设计工程技术研究中心, 北京 100190
Author(s):
ZHAO Xuying1 LI Huan1 WANG Xiaoqin2 WANG Donglin2
1. College of Computer and Control Engineering, University of Chinese Academy of Sciences, Beijing 100190, China;
2. National ASIC Design Engineering Center, Institute of Automation, Chinese Academy of Sciences, Beijing 100190, China
关键词:
协处理器架构通信处理器二维配置工作模式私有参数总线互连功耗带宽占用比调度频率
分类号:
TN92
DOI:
10.11990/jheu.201706012
文献标志码:
A
摘要:
针对当前主流通信协处理器架构存在互连网络功耗较大、调度频繁等问题,提出一种面向通信处理器的新型二维可配置协处理器架构。第一维配置为工作模式和协处理器公共参数配置,由主处理器发起,协处理器实时响应;第二维配置为加速引擎私有参数配置,由主处理器离线完成。通过功耗评估模型,该架构总线互连网络功耗仅为主流通信处理器架构的1/3;对于无线通信标准数据帧处理,总线带宽占用比由6.88%降到2.05%。基于此架构,对面向基站的无线通信接收端协处理器进行了设计实现。在数据吞吐方面与TMS320C6670中加速引擎对比,其中viterbi译码器加速比为3.3,turbo译码器加速比为2.8,可满足人们不断增长的高速数据传输需求。

参考文献/References:

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备注/Memo

备注/Memo:
收稿日期:2017-6-6。
基金项目:国家科技支撑计划(2014BAH32B00);中国科学院战略性先导科技专项(XDA06011000).
作者简介:赵旭莹(1988-),女,博士研究生;王东琳(1956-),男,研究员,博士生导师.
通讯作者:王东琳,E-mail:donglin.wang@ia.ac.cn.
更新日期/Last Update: 2018-12-01